It is necessary to perform memory diagnosis at least once a day in embedded systems, such as emergency-stop sequence-control apparatuses, for which high reliability is demanded. Therefore, there has been a need for a memory diagnosis system that is fast and that has high diagnostic accuracy.
A coupling fault is a type of failures in a memory (RAM) in which when data is read or written from or in a memory cell, data values of other memory cells change. Methods such as Walkpath or Galpat (Galloping Pattern test) can be used to diagnose a coupling fault. In Walkpath, zeros are uniformly written in all the memory cells of a memory area to be tested. Then, data in a certain target memory cell of one bit is inverted to 1, and it is checked whether the data in the remaining memory area (background) are correct. The target memory cell is then read again to check whether the data in the target memory cells is correct, and if the data in the target memory cells is correct, the data in the target memory cell is inverted back to zero. This process is repeated for all the memory cells in the memory area. Then, 1 are uniformly written in all the memory cells of the memory area and the same process is repeated. Thus, in Walkpath, one inverted element is inserted into a memory area in which data are uniformly written, and whether data of all the remaining cells are correct is checked. In Galpat, unlike Walkpath, each time a memory cell other than a target memory cell is read, the inverted memory cell (target memory cell) is read to check whether the data in the inverted memory is correct.
Another conventional memory diagnosis method is described in Patent Document 1, for example. In the method described in Patent Document 1, test data AAAAh are written at addresses 55h and AAh in a memory, test data 5555h are written at the other addresses, and then data are successively read from the memory. Data read from the address 55h or AAh is compared with the test data AAAAh, and data read from the other addresses are compared with the test data 5555h. When these data coincide with each other, the memory is determined to be normal, and when these data do not coincide with each other, the memory is determined to have a failure. In the method of Patent Document 1, if the memory has a failure in which the 7-th bit is fixed to zero, for example, the original address AAh will change to 2Ah. Accordingly, the test data AAAAh is overwritten at the address 2Ah, so that the data AAAAh is read and output from the address 2Ah. Thus, the data will not coincide with the expected value 5555h, and therefore a failure of the corresponding address line can be detected.
Patent Document 1: Japanese Patent No. 3570388